Research

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Here is a compilation of my research outputs. The most relevant outcomes such as papers, IP, and projects are linked bellow. Also, you will find some interesting material related to what I have been doing lately.

Education & Degrees: PhD Thesis and MSc Dissertation

Intellectual Property

(2017) R.D. Oliveira; D. G. Mesquita; P. F. Rosa; G. T. Hashimoto. 

                Patent. "HARP - High Availability Router Protocol". Registered Software.  Language: Hardware Description Language (VHDL). Registered by: National Institute of Industrial Property (INPI). Brazil, 2017.

Selected Bibliographical Production

Link available by clicking on the title.

Projects and Internship

Researcher

AirQKD establishes a UK ecosystem, from single-photon components to networked quantum systems, to protect short to mid-range communication in free space. In particular we carry out pilot demonstrations of the enabling infrastructure for quantum-secure 5G and autonomous and connected vehicles.


Researcher

Funded by UKRI, Quantum Data Centre of the Future is one of 12 successful bids to receive a share of the £50m funding programme for UK quantum industrial projects from UKRI’s £170 million Commercialising Quantum Technologies challenge. The QDCF brings experts in classical data centres and networking together with experts in quantum computing and quantum communications, to develop the first blueprint for a quantum data centre..


Researcher

The Quantum Communications Hub, funded through the UK National Quantum Technologies Programme, is a major collaboration of universities, numerous private sector companies and public sector bodies brought together to accelerate the development and commercialisation of quantum secure communications technologies and services at all distance scales


Researcher

A unified network, Computational and stOrage resource Management framework targeting end-to-end Performance optimization for secure 5G muLti-tEchnology and multi-Tenancy Environments. We have been designing and prototyping an FPGA-based programmable transport optical solution.


Researcher

Developing solutions based on FPGA and Software Defined Network to enable the interface between  a programmable Network Interface Card and QKD systems for multiprogrammablity in secured optical transmissions.


PhD Student

Doctoral internship aimed to discuss and develop hardware security techniques for a SDN switch operating with a Workspace-based architecture (ETArch). First, I investigated and implemented crypto mechanisms, including Montgomery multiplication, intending to add them to a future switch. Then, we decide to move the efforts to the forwarding engine of this switch itself.  A NetFPGA 1G board was used at first. I simulated a series of VHDL coded blocks that, afterwards, became Datapaths of the switch’s forwarding plane.


PhD Student

The project aimed to develop a reconfigurable architecture for Future Internet, where SDN mechanisms are applied in the network infrastructure to provide efficient video support. My duties were to be working as a hardware designer to propose a way to enable the communication between application requirements and a non-TCP/IP link layer (from the Entity Title Architecture - ETArch). I designed a switch forwarding engine based on virtual data planes with a set of hardware implemented functions and specified a protocol to configurate this switch. Also, I provided a hardware abstraction layer to be used by comunnicating entities. The whole system was prototyped in reconfigurable hardware, using a low cost FPGA of the family Altera Cyclone II. To bypass MAC and Ethernet controllers, switch ports were connected with external RJ45 transceivers completely raw of protocols. Hence, all the hardware manipulation is written in ETArch specifications, including a novel medium access controller.


PhD Student

A series of initiatives aimed to build a research partnership between two Brazilian Universities focused on electronics applied to defense, including research on hardware security in network equipments. I mainly had to evaluate whether some hardware implemented mechanism could be added at the link layer of a Future Internet architecture to improve security at the link layer level. I proposed and implemented in VHDL a mechanism to have hardware programmable Workspaces in a way that crypto algorithms could be inserted if needed. Also, I worked by training students to prototype using Xilinx and Altera’s FPGAs.


MSc Student

This project aimed to address and circumvent the Split-Brain problem in High Availability protocolos, such as VRRP. My tast was to develop a high availability protocol with no Split-Brain condition to operate in IPv4 networks and, afterwards, be compatible with ETArch to Future Internet. As a M.Sc. student, I specified the High Availability Router Protocol (HARP). The protocol spec includes environment, services, vocabulary, format and procedure rules. I built a FSM and wrote a verification model with the specification language TLA+. I implemented the protocol in VHDL simulated with Modelsim, and built a network based on the NIOS II processor to validate the protocol operation. To integrate the protocol and processor cores, I also wrote a VHDL Ethernet interface controller to act between CPU and the I/O subsystem.


Awards and Honours

Remarkable Events


Other Productions

Further details can be found in Curriculum Vitae Platform Lattes.