FPGA Projects

This is a compilation of FPGA projects I worked on as an FPGA Engineer and Researcher. Please drop me a message if you want to know a bit more about any of them, I'll be more than happy to chat. Also, send me an email if you do not have access to the related documents.

Summary

• 10 Gbps MACsec Programmable Hardware Encryption (QKD-enabled)

• Network Switching for Time-Shared Optical Networks and Distributed Quantum Computing

• 100 Gbps AES-128/192/256 Programmable Hardware Encryption (QKD-enabled)

• High Precision Timing Solution based on a Time-to-digital (TDC) converter for the 5G Fronthaul.

• Workspace-based Switch for a Future Internet Architecture

• Embedded system based on NIOS-II CPU: SoPC with the High Availability Router Protocol (HARP)

It was showcased in a live demonstration at BT Group's R&D centre - Adastral Park, during the demonstration day for the ‘Quantum Data Centre of the Future’ (QDCF) project.

Firstly, I designed and implemented a fully programmable 10G MACsec hardware to encrypt Ethernet frames. After that, I integrated the core into a network controller (NoC) within the FPGA to provide the capability of network switching with and without encryption inside the chip. Lastly, both MACsec and NoC cores prototyped in an Ultrascale FPGA (VCU 108 board) have been deployed in a standard IP network, connected to a 10GbE Ethernet switch in the edges of a 5G metropolitan network in the city of Bristol/UK. An FPGA Mezzanine Card with SFP interfaces, attached to the board via high-performance connectors, linked the chip to the optical links. A control unit with a dedicated instruction set architecture (ISA) has also been developed to allow configurations from the software controller in both network and encryption cores inside the FPGA.  The ISA is exposed via PCIe interface to the software domain.

From the management and orchestration sides, server and clients were written in Python on top of REST API services, allowing remote orchestration via the Internet. When a client requests any change to be made in the FPGA or wants to read any data (for example, switching table or MACsec parameters), an HTTP request is sent to the server. Upon receiving a request, it is translated into lower-level instructions. The server transfers data to the FPGA Controller, written in C, via subprocesses, shared memory, and files. Device drivers, also written in C, handle data to and from the FPGA. Shell and TCL scripts automate parts of the process and facilitate the lower-level data exchange between host and card.

Related Documents: 

Documents are not yet publicly available but I am happy to explain a bit more about this project and the nuances of implementation and system integration.

Main interfaces & communication protocols:

• Programming Languages: VHDL, Verilog, C, Python, TCL, Shell.

• AMD/Xilinx Ultrascale FPGA (VCU 108 board)

• Ethernet

• AXI4-Stream

• AMD (Xilinx)IP cores:

  • 10 Gbps Ethernet MAC Subsystem

  • 10 Gbps Ethernet PCS/PMA Subsystem

  • 100 Gbps Ethernet Media Access Controller (CMAC) Subsystem

  • DMA for PCI Express (PCIe) Subsystem

  • FIFOs, Width-converters, etc

• SFPs and QSFPs

• FM-S18 Octal SFP/SFP+ transceiver FMC

• GTY and GTH transceivers, SFPs, and QSFPs

• Optical Cross-Connect (OXC) from Polatis

• HTTP with REST API

• Quantum Key Distribution (ETSI 014)

This is an outcome of the work developed at the University of Bristol. In this project, I designed and implemented in FPGA a network operation controller to aggregate and disaggregate traffic among several 10 Gbps optical links and a 100 Gbps optical link. Data traveling end-to-end are formatted as Ethernet frames. To handle the forwarding mechanism, Xilinx/AMD IPs for both 10G and 100G subsystems have been instantiated and combined with FIFOs and user logic. The development kit VCU108 was utilized as hardware platform with an FPGA from the Ultrascale family and an FMC attache via HPC connectors. I have also designed a soft CPU to provide an instruction set architecture dedicated to network control. On the control side, a software controller was architectured to communicate with the embedded system via PCIe interface, set configurations, and read data from the FPGA. Still on the software side, a REST-style architecture was implemented to allow remote control of the whole system. I deployed the system with several use cases, but these two will convey the essence of it:

Related Documents: 

• [INFOCOM, 2023] Deterministic and Low-Latency Control for Distributed Quantum Computing 

• [OFC, 2022] Resilient and Quantum-Secured Time-Shared Optical Network

Main interfaces & communication protocols:

• Programming Languages: VHDL (RTL and Testbench), Verilog, C, Shell Script, and Python.

• AMD/Xilinx Ultrascale FPGA (VCU 108 board)

• Ethernet PHY, Ethernet MAC, IP protocol

• AXI4-Stream

• AMD (Xilinx)IP cores:

  • 10 Gbps Ethernet MAC Subsystem

  • 10 Gbps Ethernet PCS/PMA Subsystem

  • 100 Gbps Ethernet Media Access Controller (CMAC) Subsystem

  • DMA for PCI Express (PCIe) Subsystem

  • FIFOs, Width-converters, etc

• FM-S18 Octal SFP/SFP+ transceiver FMC

• GTY and GTH transceivers, SFPs, and QSFPs

• Optical Cross-Connect (OXC) from Polatis

• HTTP with REST API

• Quantum Key Distribution (ETSI 014)

In this project, under the leadership of a colleague, we demonstrated a QKD-enabled reconfigurable hardware encryptor/decryptor system of up to 100 Gbps Ethernet bandwidth, which provides flexibility by allowing different encryption schemes and interfaces for key generation sources to co-exist together for multiple clients in the same chipset. We implemented it in an Ultrascale FPGA. The encryption library comprises XOR, Camellia, and AES-128/192/256. Reconfiguration times of 24.1 ms and 16.7 ms were reported for the decryption and encryption blocks. The highest reconfiguration rate was reported as 676.01 CLB/ms. Our Camellia-256 implementation, the encryption latency was observed between [243.2 ns : 966.4 ns], and, the total system latency could be as low as 817.6 ns for an Ethernet frame. 

Related Documents: 

• [ECOC, 2022]

• [JOCN, 2021]

Main interfaces & communication protocols:

• Programming Languages: VHDL, Verilog, C, Python.

• AMD/Xilinx Ultrascale FPGA (VCU 108 board)

• Ethernet

• AXI4-Stream

• AMD (Xilinx)IP cores:

  • 10 Gbps Ethernet MAC Subsystem

  • 10 Gbps Ethernet PCS/PMA Subsystem

  • 100 Gbps Ethernet Media Access Controller (CMAC) Subsystem

  • DMA for PCI Express (PCIe) Subsystem

  • FIFOs, Width-converters, etc

• SFPs and QSFPs

In this collaborative project, under the leadership of a colleague, my focus centered on integrating a high-precision timing solution into the transport network for a 5G Fronthaul deployment. A time-to-digital (TDC) converter, based on delay-line architecture, was implemented in a Xilinx/AMD Ultrascale FPGA. In essence, the TDC core samples an input signal and translates the pulses into digital time information (dubbed timestamps). The timestamps are then transferred via Ethernet to the other nodes in a network aiming at synchronization. Initially, the system served to timestamp signals generated by a waveform generator, and subsequently, it was employed to timestamp eCPRI frames. This solution has achieved 11.4 ps precision on a single FPGA chip, and a synchronization channel between 2-FPGAs was established with a precision of 16.2 ps. Also, the solution managed to synchronize the nodes in a 2-node network with a precision of 21.2 ps. Data was exchanged between FPGA and PC via PCIe interface.

Related Documents: 

• [OFC, 2023]

Main interfaces & communication protocols:

• Programming Languages: VHDL, C, Shell Script, Python, and Matlab.

• AMD/Xilinx Ultrascale FPGA (VCU 108 board)

• Ethernet, eCPRI

• AXI4-Stream

• AMD (Xilinx)IP cores:

  • 10 Gbps Ethernet MAC Subsystem

  • 10 Gbps Ethernet PCS/PMA Subsystem

  • 100 Gbps Ethernet Media Access Controller (CMAC) Subsystem

  • DMA for PCI Express (PCIe) Subsystem

  • FIFOs, Width-converters, etc

• SFPs and SMA connector

In this project, I designed and prototyped the forwarding engine of a network switch for a non-TCP/IP network architecture in the context of Future Internet. The design was implemented in VHDL and prototyped in the FPGA-based academic board DE2 for proof of concept. Raw 10/100Mbps RJ-45 connectors have been utilized to enable control of the lower Ethernet MAC sublayer, reading directly from hardware registers. The whole project, as detailed in the arhitecture's figure below, comprises four datapaths implementing virtual plans for data forwarding and a series of cores for a "workspace-based" mechanism. I am the author of all the wholoe project, including writing every component, designing the interfaces and interconnecting them in a complex design serving as a proof of concept for the switch. It is a computational system comprising control unit, memory elements and operational pipelines. Each component handles several stages of pipeline. Due to constraints of the low-cost Cyclone II FPGA, the design was adapted for minimal resource consumption (with the expense of buffering capacity of drop in performance)

Related Documents: 

• PhD's Thesis 2019

• [CLOSER, 2019]

Main interfaces & communication protocols:

• Programming Languages: VHDL (RTL and Testbench), and C.

• Ethernet PHY, Ethernet MAC, Entity Title Architecture

• MII Serial Management Interface (MDC and MDIO)

• DP83848C Ethernet Physical Layer Transceiver

• LEDs, Dip Switches, GPIOs, LCD display

In this project, I specified the five elements of a new network protocol (assumptions about environment, services, vocabulary, format, and procedural rules in the format of finite state machine), dubbed as High Availability Router Protocol (HARP), for routers in highly available networks. The protocol HARP was implemented in VHDL and prototyped in the FPGA-based academic board DE2 for proof of concept. To validate HARP's operation, I built a System on a Programmable Chip (SoPC) where the main processing unit was Altera's NIOS II CPU, and the protocol was included as a peripheral mapped in memory. Several IPs were also included to form the computational system, and you can see in the video below how all IP cores have been instantiated and co-located in the SoPC. The interface between software and hardware was handled in C with the help of the Nios II C-to-Hardware Acceleration (C2H) Compiler. The detailed architecture is described in my Master's dissertation linked below (in Portuguese). The whole SoPC (HARP included) took almost 30% of the low cost Cyclone II FPGA. Meanwhile, the HARP instance alone consumed resources according to the table below. 

Related Documents: 

• Master's Dissertation 2013

• [AICT, 2013]

•  Intelectual Property (Issued by INPI Brazil) 2017

Main interfaces & communication protocols:

• Programming Languages: VHDL (RTL and Testbench), Verilog, and C.

• Ethernet PHY, Ethernet MAC, and IP

• JTAG UART

• PLL, Avalon bus, SDRAM, Flash Memory

• NIOS II soft processor and Nios II C2H Compiler 

• DM9000A: Ethernet controller with General Processor Interface